Nested Sub Blocks
This will be pretty epic if (when) I pull it off.
The plan is to have nested circuit blocks. This is no different to implementing recursive functions, just have to keep in mind the speed burden and how to inform the user of problems.
How to inform the user of problems
If a problem is encountered in a deep iteration of a nested sub block compilation then we want to bust out of it and output a popup alert on the main GUI. This is best implemented with access to the main scene node via an auto-load singleton I think.
So I added a main
var to the Data
autoload where the main scene may store a reference to itself during its setup.
Also, I moved the general code for loading data from disk to this Data
autoload script where we may want to load data without the involvement of a GUI.
So now, the access to the main scene alert popup code is available simply as Data.main.alert("Message")
. And we can return back an ok
value up the tree to indicate success or failure to the original calling function rather than signals which would be like falling apples but going upwards.
Compiling
For the sub blocks there is no need to care about configuring slots of the GraphNode
, so we will pass a parameter about that need in the add_pins
function that kicks off the setup of the block. And we will load the circuit data from disk to load the latest version of the sub block circuit (maybe cache this data?).
So have to carefully set this up and test it next.
More Devlog entries
Most recent first
- 2021 10 02 New Release of Digital Logic Simulator
- 2021 08 27 Debugging with a log file
- 2021 08 26 Testing Circuit Blocks
- 2021 08 24 Bug Fixing with Blocks
- 2021 08 22 Debugging Circuit Blocks
- 2021 08 21 Circuit Blocks Update
- 2021 08 18 Circuit Blocks
- 2021 08 16 Highlighting of wires
- 2021 08 12 Adding Tutorial Content
- 2021 08 07 Numbers Scene
- 2021 08 06 Numbers Tabbed Scene
- 2021 08 04 Number Display Widget
- 2021 07 26 Logic Simulator Update
- 2021 07 24 - Launch of V1.0
- 2021 07 23 - Truth Tables
- 2021 07 22 Progress Update
- 2021 07 21 - Simple Computer Simulation
- 2021 07 16 - Community Forum
- 2021 07 15 - Community News
- 2021 07 11 - Save and Load ROM Data
- 2021 07 09 - Documentation About The Logic Simulator
- 2021 07 08 - Big Progress
- 2021 07 07 - RAM and ROM Testing Complete
- 2021 07 06 - Implementing Tests
- 2021 07 05 - Cool algorithm for binary text string
- 2021 07 04 - Debugging Complex Situations
- 2021 06 30 - End of June - Refactoring Continues
- 2021 06 29 Community
- 2021 06 28 Implementing More OOP
- 2021 06 27 Memory Parts
- 2021 06 26 Improving the Memory Manager
- 2021 06 25 Memory Data
- 2021 06 24 Memory Management
- 2021 06 23 First Devlog Entry