Bug Fixing with Blocks
Yesterday I was testing out blocks (sub-circuits) and getting really confused over what was causing some bugs so decided to leave it until today.
It’s good to take a break when you are stuck.
So, today I started by creating simple circuit examples and turning them into blocks and playing with them. This was a great way to fully understand what was going on and to fix the bugs.
The problems that I identified:
- Connections coming into a block have an external port number to a pin, but the pin output is on port zero internally
- Connections going out from a block need to know what external port they connect to
The first problem was a simple fix to simply set the port number to zero when initially calling the internal level/value propagation logic.
The second problem was solved by setting a data value on each IO node specifying its external port number at the time of compiling the block.
Then I continued testing encapsulating the various parts such as ALU as a block and testing the circuit with input pins surrounding the block against its truth table.
I came up with an efficient procedure to set up these test circuits which I should explain in a manual at some stage.
Common way to alert about unsaved changes
After thinking about warning players about having unsaved changes I implemented a Yes/No popup window which replaced the standard Confirm Dialog. This was used for when quitting the game and for when going to wipe the scene or load another circuit before saving changes. This provided a consistent and nice interface that actually pops up the save dialog depending on the choice of the user.
Now this could be a great topic for a tutorial.
Massive progress today. But I haven’t thought much about implementing nested sub-circuits. Maybe it will be unnecessary or impractical? Have to see.
More Devlog entries
Most recent first
- 2021 10 02 New Release of Digital Logic Simulator
- 2021 08 28 Nested Sub Blocks
- 2021 08 27 Debugging with a log file
- 2021 08 26 Testing Circuit Blocks
- 2021 08 22 Debugging Circuit Blocks
- 2021 08 21 Circuit Blocks Update
- 2021 08 18 Circuit Blocks
- 2021 08 16 Highlighting of wires
- 2021 08 12 Adding Tutorial Content
- 2021 08 07 Numbers Scene
- 2021 08 06 Numbers Tabbed Scene
- 2021 08 04 Number Display Widget
- 2021 07 26 Logic Simulator Update
- 2021 07 24 - Launch of V1.0
- 2021 07 23 - Truth Tables
- 2021 07 22 Progress Update
- 2021 07 21 - Simple Computer Simulation
- 2021 07 16 - Community Forum
- 2021 07 15 - Community News
- 2021 07 11 - Save and Load ROM Data
- 2021 07 09 - Documentation About The Logic Simulator
- 2021 07 08 - Big Progress
- 2021 07 07 - RAM and ROM Testing Complete
- 2021 07 06 - Implementing Tests
- 2021 07 05 - Cool algorithm for binary text string
- 2021 07 04 - Debugging Complex Situations
- 2021 06 30 - End of June - Refactoring Continues
- 2021 06 29 Community
- 2021 06 28 Implementing More OOP
- 2021 06 27 Memory Parts
- 2021 06 26 Improving the Memory Manager
- 2021 06 25 Memory Data
- 2021 06 24 Memory Management
- 2021 06 23 First Devlog Entry